Universal Properties of NOR and NAND Gates
Articles,  Blog

Universal Properties of NOR and NAND Gates

>>Good day. This is Jim Pytel from Columbia
Gorge Community College. This is Digital Electronics One. This lecture is entitled
Universal Properties of NAND and NOR Gates. We have discussed a bunch
of basic logic gates. We first discuss the
AND, the OR and the NOT and then we introduce
the NAND and the NOR and their negative logic
equivalents to negative AND and the negative OR. And then we also introduce
the EXOR now that’s exclusive OR exclusive NOR gate. I showed you how you can
make all of those other gates with combinations of the
AND and the OR and the NOT. However, what if I was tell you
it’s not really done that way. You use another basic
component to make the ANDs and the ORs and the NOTs. And if that’s true, if that one
basic component is making those basic gates it sounds like
what I’m trying to tell you is that one basic component hooked up in different configurations
is making any logic circuit that we can possibly create. What it really is you’re
actually making is these NAND and NOR gates. What’s inside a NAND
and a NOR gate? Well for this course
you don’t need to know. For some of our connective
devices and circuits you’re going
to crack these things open. You’re going to make
one of these things. It’s super simple
what’s inside that. That’s why you use the
NANDs and the NOR gates. They’re super simple to make. They’re super simple
to mass produce. And if you can hook them up in different configurations
you can create a NOT, an AND and an OR. You can use a NOT, AND and OR. You can make a NAND. Well you’ll see it’s easier. I would say how do
you make an AND out of a NAND, you just use a NAND. You don’t have to do
anything funky with that. A NOR, a negative OR a negative
AND exclusive OR, exclusive NOR and you take all of these
things and crazy combinations and build higher functional
combinational logic circuits. And sequential for that this
lecture is going to be two easy. It’s an incredibly important
topic but it is too easy to understand what I’m
going to talk about here because you guys are experts
by now and you can go ahead and spit out the truth table
for a NAND and for a NOR without looking at
your cheat sheet. And if it took you longer
to write that truth table on your note pad, because you’re
actively listening to this thing than it took me to copy
and paste it, then you need to go back and look at
the NAND and the NOR gate. If you’re still looking
this thing up right now you
got some work to do. You need to know how
these things work. When I say no, you
need to be able to at a moment’s notice spit out
the truth table for these things without consulting
some resource. That being said, I’m going
to leave the NAND gate and the NOR gate’s truth table
here for those individuals that potentially need some
assistance we may be even consultingly six. So, the universal properties of
the NAND and NOR gates essential to this is obviously you
understanding the NAND and the NOR gates and
how they work initially. But I’ve already referred
to this in the NAND and NOR gate lectures. This guy how do I make a NOT
gate using just a NAND gate. Let’s just stick to
the NANDs right now. How do I make a NOT gate? Alright this is take a NAND. It’s got two inputs. Tie its inputs together and
put a digital data set on it, up down up down up down. What are the two inputs getting? It’s getting the same value. So when it’s zero, when that
waveform A is zero what are the two inputs getting? Zero and a zero. Look at the truth table. It’s getting the
zero and a zero. What’s my output? A one. Oh my gosh
it’s inverted it. When that digital data is
getting a one what are my two inputs getting? A one and one where
on my truth table? If a one and a one are on
the inputs what’s my output? Zero. Oh my gosh,
it’s an inversion. So if a NAND gate with its
two inputs tied together it is functionally equivalent
to a NOT gate. And if you can understand that
you can build an AND gate. And if you can understand
that you can build an OR gate. Okay, I’m challenging you
to go ahead and do that. If this is true right here,
if I can swap out a NOT gate for a NAND gate with its two
inputs tied together how can I create an AND gate
of just NAND gates? And I need you to
pause the lecture. I need you think about this. How do you do it? If you pause the lecture
you’d probably come up with the following action
given the NAND gate really is functionally equivalent
to an AND gate with its output inverted, right. So it’s A, B what is this? It’s A AND B. Well
it’s A AND B inverted. You may be using rule
nine which states that A, something inverted,
inverted again is equal to A. Why not put
another inverter here? So if this thing is a NAND
gate and I can make an inverter out of another NAND gate
what’s that look like? It looks like this, NAND
gate inputs A AND B output into another NAND gate with
its inputs tied together. That’s your AND gate, functionally equivalent
to an AND gate. Don’t believe me, put
it in the truth table. AB zero zero, zero
one, one zero, one one. What’s the output
of the NAND gate? A AND B inverted what
is the truth table? Don’t even look it up. One one, one zero. The only time it’s low is
when all inputs are high. What is this guy? Well it’s getting one and a
one for this first thing here. When it’s getting
a one and a one where are we on this
truth table? A zero, a zero. Now we’re getting over here
both inputs are getting a zero. What’s their output? Output is a one. What’s that truth
table look like? Well it’s A AND B
inverted, inverted again. What’s double inversion? A AND B. What’s that
truth table look like? It looks like an AND gate. Okay this is really cool and what you do is
just use this thing. Think of this thing as a box. And here is a box with inputs
A and B on the left hand side. I’ll put X on the right and
I know there’s a NAND gate in there feeding
under the NAND gate with its two inputs
tied together. But what’s it performing? So same thing as
what’s inside this box. It’s got two inputs
A AND B on the left and an output X on the right. And it’s performing that same
truth table as an AND gate. Let’s just take it a
little step further here. Okay, we’ve talked about using
a NAND gate as an inverter. Now we talked using
the NAND gate in different combinations
to make AND gate. This is a little bit tricky. How do I make an OR
gate out of a NAND gate? So look at our little symbols
here which we’ve drawn. I want you to find the
negative logic equivalent of the NAND gate. The negative logic equipment for a NAND gate is this guy
right there, the negative OR. See if you can take a negative
OR which is NAND gate and see if you can make a, excuse
me an OR gate out of that. Hopefully your drawing
looks like this. Okay so there is my negative OR. I use an OR with
its inputs inverted. How do I get rid of
that inverted input, inverted again right there? Well I just told you that
I could take a NAND gate and tie its inputs together
to make an inverter. What am I creating here? Because a negative OR
is equivalent to a NAND. I’m creating a functional
equivalent of an OR gate inside a box ABX. I look at this from
the box inputs A AND B of an output X that’s
functionally equivalent to an OR gate inside a box. Don’t believe me? Go ahead and try it out. So I got A. I got B. What
is happening to A AND B? I’m inverting them. NOT A, NOT B, pen issues. What’s happening to NOT
A and NOT B. So NOT A, NOT B. I’m ANDing them together
and then inverting the result. I’m basically doing
the NAND of this. The output is low when all
inputs are high right there. What’s that truth
table look like? That looks like OR
gates truth table. The output is high
when any input is high. And I’m saying this is
the input right here because that’s what I
originally start with. Don’t think of this as
the input because we’re on this side of the box, okay. That is how you make AND gates. That’s how you make NOT
gates, AND gates and OR gates out of just the NAND okay. And there’s something you might
want to put on you cheat sheet but man it is so easy. It’s so easy. You don’t even need to put
that on your cheat sheet because you already know
what I’m talking about. A NAND with its imputs tied
together that’s a NOT A. A NAND feeding a NAND based
inverter, that’s an AND. A NAND with its inputs inverted
with a NAND based inverter, that’s the functional
equivalent to a OR gate. So I just showed you how to do that with NAND gates,
not challenge it. Figure out how you do
that with NOR gates. And I’m going to throw a bone
to you what is a NOR gate with its inputs tied together? If you can understand
this it should be too easy to create a NOT gate. It should be too easy
to create an OR gate. It should be too easy
to create a NAND gate. Okay if you’ve done
what I’m asking you to do what is a NOR gate with
its two inputs tied together? Let me clean up because I was
talking about NANDs to that. Okay there you go. If I’ve got a digital data
signal coming in up down up down up down it’s
taken the value zero. What are the two inputs getting? It’s getting a zero and a zero. What’s my output? One, okay. I’ve inverted it. Now it’s a one. Both inputs are getting a one. My output is zero. I’ve inverted a NOR with
its inputs tied together. Functionally equivalent
to an inverter. How do I make an
OR out of a NOR? Well, it a NOR is an inverted OR you’re basically ORing
something then inverting it, why not reinvert the output
using a, you guessed it, a NOR with its inputs tied
together functionally equivalent to an OR gate. If a NOR is equivalent
to a negative AND, it’s negative logic
equivalent, how do I make an AND out of just NOR gates? Well take the negative logic
equivalent, a negative AND and invert the inputs. But I want to use just NORs. Take a NOR and tie
its inputs together. Take a NOR and tie
its inputs together. And since I want to use
this same symbol it’s going to look like this. And there’s the whole
cheat sheet. You’ve got your NOR with
its inputs tied together. It’s functionally
equivalent to a NOT. Got a NOR with its
output being inverted with a NOR based inverter
that’s equivalent to an OR. And then we’ve got an
AND gate which is a NOR with its inputs inverted
using NOR based inverters. So this is really neat. You’ve got many different
logic functions all formed from this same gate. This is, everybody in your squad
is shooting 5.56 ammunition. No one’s got some crazy
weird caliber musket ball that you can’t use
in your rifle. It’s the same piece of
equipment used over and over in different combinations so you can perform crazy
different logic functions. Hopefully this is easy for you. This should be, it should have
been a pretty easy discussion. No use beating a dead horse. Let’s just see if we
can apply this thing. Just take a logic circuit
and see if you can make that same logic circuit using
just NANDs or just NORs. Here’s an example right here. Okay here’s our, put our cheat
sheet off to the left hand side. I don’t know if you need it
but let’s go ahead and see if you can for the
output X right there, for that particular
logic circuit for a three input logic circuit. Go ahead and see if you can
create a NAND equivalent. What I’m going to do to do this
is draw a box around the OR, draw a box around the AND. Take out the contents of the box
and put in the NAND equivalent of what was in the box. It should look like this. It’ll make our life ever so slightly more easy,
make that a red box. There you go. Too easy to do the exact
same thing, try to implement that circuit using
just NOR gates. You should look at something
like this and there you go. That is the NOR equivalent of
the original circuit we started with and that’s kind of, that’s
what I would call correctish. It’s correctish. Yes, it’s performing the
output X like we’d expect and I dare you guys
to do the truth tables for the original one,
for the NAND based logic and then for the NORs. It’s going to come up
with the same truth table and the expression used. These are great,
great opportunities to do some De Morgans’
theorems and Boolean and logic simplification. However, there exists
something in this bottom circuit at the NOR based circuit that
I could potentially simplify. And when I say make this
circuit using just NOR gates, I need to actually kind of insert a kind of
qualifier to that. Use a minimum number
of NOR gates. Is there something
in our lower circuit that we could potentially
save some connections? And what I’m referring
to is right here. What is this guy doing? Well it’s a NOR gate with
its inputs tied together. What’s that? It’s a NOT gate. What’s this guy? It’s a NOR gate with its
inputs tied together. What is it doing? It’s acting like an inverter. Why in the heck’s name
am I taking a signal, inverting it, uninverting it. Okay, what am I using there? I’m using rule nine,
the double inversion. Sounds like it can
save some connections, forget those two NOR gates. What does my simplified
circuit look like? It looks like this. There you go. Problem with that though is
I can’t really define them in the red boxes and the
blue boxes like I did before. If I had purple, one of
my least favorite colors, what would I have to do is
just do an overlap right there. If I required that intermediary
signal I’ve kind of lost it in this implementation. Go ahead and see if you can
come up with, see if I said that these are great
opportunities for multilevel circuit analysis
and De Morgan’s theorem. Try to do the De
Morgan’s theorem. [inaudible] with some
Boolean simplification. Same thing for that. You should come up with the
same results and this one too. Try one more example of this and
then just put this topic to bed. I mean this is too easy. Just take the box, take the
contents out of the box and put in the box the equivalents. Try one more. Okay so here’s another
example that’s like a four input
circuit this time. And I’m going to give you
a challenge on this one. You can, yeah you
should instantly go for yeah, that’s easy. But I’m going to give you
a challenge this time. You can only use two
input NAND gates. Okay, so try to input this
circuit using just two input NAND gates. Try to implement the circuit
with just two input NOR gates. Okay, so hopefully you’ve come
up with something like this. Well first off, how do
I make this circuit? I’ve got three input AND gate. Don’t worry about the
NAN conversion right now. How do I make a three
input AND gate out of just two input AND gates. It should look something
like this. Okay, so what is
coming out of here? A ANDed with NOT B.
What’s come out of here? C OR D. What is this
last AND gate doing? It’s ANDing A AND B with C OR D. That’s the same expression
that’s happening here. It’s taking A ANDing
with B. Excuse me, ANDing with the results
of C OR D. Same expression and what I’ve done is I’ve
created a three input AND gate out of two nested AND gates
using the associative property of AND gates, okay. So that might help
out a little bit. Go ahead. See if you can come
up with a NAND equivalent. Hopefully it should look
something like this. And there you go, there’s
the NAND equivalent. There are opportunities
for some, actually let me just draw
this here quick for you. Where is the inverter for B? It’s that one or it’s this
AND gate it’s that one. OR gate it’s this one. Basically just taking
the contents of the box and just putting in the
NAND’s equivalent of it. Is there opportunities
for simplification? No. Can I redraw
this thing perhaps in a different fashion, maybe. You know maybe I could use like the negative logic
equivalent, the negative OR. It’s not really going
to try to help us. I know seems more complicated, but if the NAND is an
incredibly cheap part to make, it’s pretty neat that you can go
ahead and take and think of it in terms of a PLD,
programmable logic device. Here is just a sea, an
endless sea of unhooked up NAND gates stretching
out to infinity. And if I could just somehow
program these unconnected demands to perform NOT gates
and perform AND gates to perform OR gates and then take
those NAND based NOTs, ANDs and ORs to create NANDs. Well I would say you’re
not going to create a NAND out of it because it’s a NAND. NOR is exclusives ORs,
exclusive NORs and then build up to make adders
and it’s pretty cool. You know it’s a neat
way of doing things. Okay, here’s another challenge. Take the same circuit, make
a NOR based equivalent of it. Okay there is my initial attempt at a NOR based equivalent
of that. Where is the inverter for B? Right there. Where’s that first AND gate? Whoops got to change
the color, right there. Where is the OR that one? And where is my final
AND gate right there? Where in here might I be able
to simplify, reduce the number of connections that I need? And long story short it’s
always those double negations when you start looking at these
things, start looking for times where there’s an inverter,
a NOR based inverter or a NAND based inverter,
because you can do this for NANDs where they are two
inverters feeding each other. And why would you ever
do something like that? Okay so think about right
here and right there. I can remove them entirely. I don’t even need
those things, okay. Let’s go ahead and
redraw it again. So there is the same circuit
using the minimum number of NOR gates. What have I lost? I’ve lost access to
that C OR D signal. And additionally I’ve lost
access to that NOT B signal. Potentially you know
you need NOT B and C OR D for some other
logical output. You know here’s X. Here’s Y.
You may need those things. What have you gained here? Well if you don’t need those
things don’t worry about it. What have you gained? Less power consumption. If you really are
implementing these things out of fixed function of your
eight circuits, less gates. That’s it guys. I mean this is really,
really simple. You should the know the
truth table of the NAND, negative logic equipment,
the negative OR and the NOR and it’s native logical
equivalent, the negative AND. And for you to understand
this you should be able to use again Boolean rules to go
ahead and simplify this thing. If you’ve got those double
inverters feeding off each other, why would you ever
do something like that? Okay, let’s bring this
lecture to a close and move onto the next subject.


Leave a Reply

Your email address will not be published. Required fields are marked *